胡诣哲博士现任中国科学技术大学特任教授，博士生导师。师从全数字锁相环（ADPLL）、数字化射频集成电路（Digital-RF）创始人，IEEE Fellow, R. Bogdan Staszewski 教授。胡诣哲博士是“超低闪烁相噪（flicker PN）振荡器”和“超低抖动全数字锁相环”专家，发明了“电荷分享锁定（charge-sharing locking）”锁相技术，提出了“振荡器闪烁相噪”和“基于双z变量超宽带频综相噪”的统一分析技术。曾担任华为海思技术顾问（兼职）和台积电技术顾问（兼职）。目前，以一作或通讯作者发表ISSCC/JSSC 4篇，TCAS-I 1篇（入选TCAS-I 2022 Highlight），TCAS-II 3篇（含2篇主编邀稿），以及ESSCIRC, CICC, VLSI等。获欧洲专利局专利一项，WIPO专利一项（成果应用于华为基站芯片）。曾受国际电路与系统协会硅谷分会（IEEE CASS-SCV）邀请，在高通公司作一小时特邀报告；受亚洲固态电路会议（ASSCC-2022）邀请，在Rising Star Express论坛作特邀报告。担任IEEE JSSC, TCAS-I/II, TMTT等审稿人。

主要研究方向为：数字化射频集成电路设计（Digital-RF），包括但不限于：新型相控阵芯片，全数字锁相环，毫米波数字雷达，高性能振荡器，数字化功率放大器等。招收硕士研究生，博士研究生，博士后研究员，特任副研究员等。

欢迎感兴趣的同学投送简历至 huyz@ustc.edu.cn

• 2009.9–2013.7 哈尔滨工业大学，本科，电子科学与技术

• 2013.9–2015.3 复旦大学，硕士，微电子学与固体电子学

• 2015.5–2019.5 爱尔兰都柏林大学，博士，数字化射频集成电路设计

• 2016.5–2017.11 华为海思，技术顾问（兼职）

• 2018.6–2022.4 台积电，技术顾问（兼职）

• 2019.5–2020.10 都柏林大学，博士后研究员

• 2020.10–2022.9 爱尔兰微电子电路中心，责任研究员（PI）

• 2022.10–至今 中国科学技术大学，特任教授

• Y. Hu, X. Chen, T Siriburanon, J. Du, V. Govindaraj, A. Zhu and R. B. Staszewski, “A charge-sharing locking technique with a general phase noise theory of injection locking” , IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 2, pp. 518–534, Feb. 2022. 

•  Y. Hu, T. Siriburanon and R. B. Staszewski, “A low-flicker-noise 30-GHz class-F23 oscillator in 28-nm CMOS using implicit resonance and explicit common-mode return path,” IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 7, pp. 1977–1987, July. 2018. (Invited Paper)

•  Y. Hu, T. Siriburanon and R. B. Staszewski, “Multirate Timestamp Modeling for Ultra-Low-Jitter Frequency Synthesis: A Tutorial”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 69, no. 7, pp. 3030–3036, Jul. 2022. (Invited Paper)

• Y. Hu, T. Siriburanon and R. B. Staszewski, “Oscillator flicker phase noise: A tutorial”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 68, no. 2 pp. 538–544, Feb. 2021. (Invited Paper)

• Y. Hu, T. Siriburanon and R. B. Staszewski, “Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillators”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 66, no. 12 pp. 1962–1966, Dec. 2019.

•  Y. Hu, X. Chen, T. Siriburanon, J. Du, Z. Gao, V. Govindaraj, A. Zhu and R. B. Staszewski, “A 21.7–26.5GHz charge-sharing locking quadrature PLL with implicit digital frequency tracking loop achieving 75fs jitter and -250dB FoM,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), 18 Feb. 2020, pp. 276–277, sec. 17.6, San Francisco, CA, USA. 

• Y. Hu, T. Siriburanon and R. B. Staszewski, “A 30-GHz class-F₂₃ oscillator in 28nm CMOS using harmonic extraction and achieving 120kHz 1/f³ corner,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. A4L-C1, pp. 87–90, 12 Sept. 2017,Leuven, Belgium.

• J. Du, Y. Hu*, T. Siriburanon*, E. Kobal, P. Quinlan A. Zhu and R. B. Staszewski, “A compact 0.2–0.3-V inverse-class-F₂₃ oscillator for low 1/f³ noise over wide tuning range” ,IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 2, pp. 452–464, Feb. 2022. (*As corresponding authors)

• X. Chen, Y. Hu*, T. Siriburanon*, J. Du, R. B. Staszewski and A. Zhu, “Flicker Phase Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators” , IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 69, no. 3, pp. 973–984, Mar. 2022. (*As corresponding authors)

• X. Chen, Y. Hu*, T. Siriburanon*, J. Du, R. B. Staszewski and A. Zhu, “A Tiny Complementary Oscillator with 1/f³ Noise Reduction Using a Triple-8-Shaped Transformer”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 162–165, 14 Jul. 2020. (*As corresponding authors)

• J. Du, Y. Hu, T. Siriburanon and R. B. Staszewski, “A 0.3 V, 35% tuning-range, 60 kHz 1/f³-corner digitally controlled oscillator with vertically integrated switched capacitor banks achieving FoMT of -199 dB in 28-nm CMOS,” Proc. of IEEE Custom Integrated Circuits Conf.(CICC), 17 Apr. 2019, ses. 26–4, pp. 1–4, Austin, TX, USA.

• J. Du, T. Siriburanon, Y. Hu, V. Govindaraj and R. B. Staszewski, “A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL,” IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 11, pp. 3445–3457, Nov. 2021.

• J. Du, T. Siriburanon, Y. Hu, V. Govindaraj and R. B. Staszewski, “A 2.0–2.87GHz -249dB FoM 1.1 mW Digital PLL Ex- ploiting Reference-Sampling Phase Detector”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 158–161, 9 Jul. 2020.

• J. Du, T. Siriburanon, X. Chen, Y. Hu, V. Govindaraj, A. Zhu and R. B. Staszewski, “A Millimeter-Wave ADPLL with Refer- ence Oversampling and Third-Harmonic Extraction Featuring High FoM_jitter-N”, IEEE Solid-State Circuits Letters (SSC-L), vol. 4, pp. 214–217, 29 Oct. 2021.

• J. Du, T. Siriburanon, X. Chen, Y. Hu, V. Govindaraj, A. Zhu and R. B. Staszewski, “A 24–31 GHz Reference Oversampling ADPLL Achieving FoM_jitter-Nof -269.3 dB,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 18 June 2021, sec. C17-2, pp. 1–2, Kyoto, Japan (remote).