返回首页
学院概况

位置栏目

您现在的位置： 首页  师资队伍  教授/研究员  指导教师（校内）
胡诣哲特任教授
主要研究方向：数字化射频集成电路设计（Digital-RF），包括但不限于：新型相控阵芯片，全数字锁相环，毫米波数字雷达，高性能振荡器，数字化功率放大器等。
电话：
邮箱：huyz@ustc.edu.cn
办公室：


 

个人简介

胡诣哲现任中国科学技术大学特任教授，博士生导师。师从全数字锁相环（ADPLL）与数字化射频集成电路（Digital-RF）创始人 IEEE Fellow R. Bogdan Staszewski 教授，专注于数字化射频集成电路与架构的研究工作。他提出了“极低闪烁相噪数控振荡器”和“极低抖动电荷域全数字锁相环（Charge-Domain ADPLL）”技术，并系统性阐述了“振荡器闪烁相噪”与“超宽带频综相噪与杂散”机理。 目前，他以第一作者或通讯作者发表若干高水平论文，包括： ISSCC/JSSC 7篇，TCAS-I/O-JSSCS/TCAS-II 5篇（入选TCAS-I 2022 Highlight，且含3篇主编邀稿），以及VLSI/ESSERC/CICC 6篇等。胡诣哲教授曾担任华为海思技术顾问（兼职）和台积电技术顾问（兼职），拥有多项美国专利、欧洲专利局专利和WIPO专利，其研究成果已应用于华为基站芯片中。他曾受国际电路与系统协会硅谷分会（IEEE CASS-SCV）邀请，在高通公司作一小时特邀报告；并受亚洲固态电路会议（ASSCC-2022）邀请，在Rising Star Express论坛作特邀报告。同时，胡诣哲教授还担任IEEE JSSC、TCAS-I/II、TMTT等期刊的审稿人。


主要研究方向包括但不限于：数字化射频集成电路设计（Digital-RF），新型相控阵芯片，全数字锁相环，毫米波数字雷达，高性能振荡器，数字化功率放大器等。招收硕士研究生、博士研究生、博士后研究员和特任副研究员等。


欢迎感兴趣的同学投送简历至 huyz@ustc.edu.cn

个人经历

  • 2009.9–2013.7 哈尔滨工业大学，本科，电子科学与技术

  • 2013.9–2015.3 复旦大学，硕士，微电子学与固体电子学

  • 2015.5–2019.5 爱尔兰都柏林大学，博士，数字化射频集成电路设计

  • 2016.5–2017.11 华为海思，技术顾问（兼职）

  • 2018.6–2022.4 台积电，技术顾问（兼职）

  • 2019.5–2020.10 都柏林大学，博士后研究员

  • 2020.10–2022.9 爱尔兰微电子电路中心，责任研究员（PI）

  • 2022.10–至今 中国科学技术大学，特任教授

论文

  •         J. Deng, A. Li, J. Li, W. Tao, S. Yang, Z. Zhang, Y. Yang, X. Cheng, F. Lin, R. B. Staszewski, L. Lou, and Y. Hu*, “A 0.184 mm2 W-band Single-RTWO-Based Subharmonic RX Achieving 3.72-dB NF and I/Q Mismatch <0.8° in 22nm CMOS”, 2025 IEEE Symposium on VLSI Technology and Circuits(VLSI), Kyoto, Japan, 2025, pp. 1-2. (*As corresponding author)

  •          W. Tao, Y. Yang, R. B. Staszewski and Y. Hu*, “A PLL Technique: Charge-Steering Sampling,” in IEEE Journal of Solid-State Circuits (JSSC), early access, May 29, 2025. (*As corresponding author)

  •          W. Tao, Y. Yang, W. Chen, R. B. Staszewski and Y. Hu*, “A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling,” in IEEE Journal of Solid-State Circuits (JSSC), early access, May 1, 2025. (*As corresponding author)

  •          T. Lu, Z. Liu, H. Yang, S.-W Sin, R. B. Staszewski, F. Lin, L. Lou, Y. Hu*, “A 0.0022 mm2, 2 GS/s Resettable VCO-Based ADC With-out Quantization Noise Shaping,” 2025 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp. 1-4.(*As corresponding author)

  •          Y. Hu*, W. Tao and R. B. Staszewski, “Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation,” in IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 226-237, 2024. (*As corresponding author)

  • W. Tao, Y. Liu, Y. Yang, R. B. Staszewski, F. Lin and Y. Hu*, “A Compact 21–25 GHz Charge-Domain Fractional-N ADPLL with 168 fs Total RMS Jitter,”50th IEEE European Solid-State Electronics Research Conference (ESSERC), Bruges, Belgium, 2024. (*As corresponding author)

  • W. Tao, W. Zhao, R. B. Staszewski, F. Lin and Y. Hu*, An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and –252 dB FoM, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan, 2023, pp. 1-2. (*As corresponding author)

  •  X. Chen, Y. Hu*, T. Siriburanon*, J. Du, R. B. Staszewski and A. Zhu, A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness, IEEE Journal of Solid-State Circuits （JSSC）, vol. 58, no. 7, pp. 1945-1958, July 2023. (*As corresponding authors)

  • Y. Hu, X. Chen, T Siriburanon, J. Du, V. Govindaraj, A. Zhu and R. B. Staszewski, “A charge-sharing locking technique with a general phase noise theory of injection locking”, IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 2, pp. 518–534, Feb. 2022. 

  • Y. Hu, T. Siriburanon and R. B. Staszewski, “A low-flicker-noise 30-GHz class-F23 oscillator in 28-nm CMOS using implicit resonance and explicit common-mode return path,” IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 7, pp. 1977–1987, July. 2018. (Invited Paper)

  • Y. Hu, T. Siriburanon and R. B. Staszewski, “Multirate Timestamp Modeling for Ultra-Low-Jitter Frequency Synthesis: A Tutorial”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 69, no. 7, pp. 3030–3036, Jul. 2022. (Invited Paper)

  • Y. Hu, T. Siriburanon and R. B. Staszewski, “Oscillator flicker phase noise: A tutorial”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 68, no. 2 pp. 538–544, Feb. 2021. (Invited Paper)

  •  Y. Hu, T. Siriburanon and R. B. Staszewski, “Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillators”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol. 66, no. 12 pp. 1962–1966, Dec. 2019.

  • Y. Hu, X. Chen, T. Siriburanon, J. Du, Z. Gao, V. Govindaraj, A. Zhu and R. B. Staszewski, “A 21.7–26.5GHz charge-sharing locking quadrature PLL with implicit digital frequency tracking loop achieving 75fs jitter and -250dB FoM,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), 18 Feb. 2020, pp. 276–277, sec. 17.6, San Francisco, CA, USA. 

  • Y. Hu, T. Siriburanon and R. B. Staszewski, “A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120kHz 1/f3 corner,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. A4L-C1, pp. 87–90, 12 Sept. 2017, Leuven, Belgium.

  •  J. Du, Y. Hu*, T. Siriburanon*, E. Kobal, P. Quinlan A. Zhu and R. B. Staszewski, “A compact 0.2–0.3-V inverse-class-F23 oscillator for low 1/f3 noise over wide tuning range”，IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 2, pp. 452–464, Feb. 2022. (*As corresponding authors)

  • X. Chen, Y. Hu*, T. Siriburanon*, J. Du, R. B. Staszewski and A. Zhu, “Flicker Phase Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators” , IEEE Trans. on Circuits and Systems I (TCAS-I), vol. 69, no. 3, pp. 973–984, Mar. 2022. (*As corresponding authors)

  • X. Chen, Y. Hu*, T. Siriburanon*, J. Du, R. B. Staszewski and A. Zhu, “A Tiny Complementary Oscillator with 1/f3 Noise Reduction Using a Triple-8-Shaped Transformer”, IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 162–165, Jul. 2020. (*As corresponding authors)

  •  J. Du, Y. Hu*, T. Siriburanon* and R. B. Staszewski, “A 0.3 V, 35% tuning-range, 60 kHz 1/f3-corner digitally controlled oscillator with vertically integrated switched capacitor banks achieving FoMT of -199 dB in 28-nm CMOS,” Proc. of IEEE Custom Integrated Circuits Conf. (CICC), Apr. 2019, ses. 26–4, pp. 1–4, Austin, TX, USA. (*As corresponding authors)

  •  J. Du, T. Siriburanon, Y. Hu, V. Govindaraj and R. B. Staszewski, “A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL,” IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 11, pp. 3445–3457, Nov. 2021.