位置栏目

许中广特任教授
主要研究方向:新型存储器芯片、存储器可靠性、存算融合架构、AI硬件加速器和智能存储体系与架构
电话:
邮箱:xuxu@ustc.edu.cn
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个人简介

许中广,特任教授,博导,国家海外高层次青年人才。

曾任职于美国西部数据公司资深闪存研发工程师、美国美光公司主任存储架构师,并担任美光专利评委会委员。长期致力于新型存储器芯片(内存级存储SCM),存算一体架构、面向AI应用的硬件加速器和存储系统优化、智能存储系统(DPU)等方面的研究,研究成果以论文形式在多个相关领域顶级国际会议和刊物上发表20余篇(第一作者+通讯13篇),包括IEEE IEDM, IEEE EDL, IEEE JETCAS, IEEE HPEC,NANO Lett., APL, Sci. Rep,.等, 申请美国专利80余项 (授权20余项),申请中国专利22项 (授权6项,部分专利授权给长江存储)。

招聘信息:课题组常年招收硕士研究生、博士研究生、博士后研究员与特任副研究员(提供有竞争力的薪资福利待遇),欢迎感兴趣的学者投送简历至xuxu@ustc.edu.cn联系, 欢迎面谈。


个人经历

2005年-2009年,中国科学技术大学,应用物理系学士(优秀毕业生)

2009年-2012年,中国科学院微电子所,微电子学与固体电子学硕士

2012年-2016年,美国加州大学河滨分校,电子工程学博士

2016年-2019年, 美国西部数据公司,资深研发工程师

2019年-2024年, 美国美光公司,主任系统架构师

2024年-至今,中国科学技术大学微电子学院,特任教授


论文

1. Z. He, X. Jin, Z. Xu*, F3: An FPGA-based Transformer Fine-tuning Accelerator with Flexible Floating Point Format, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, DOI: 10.1109/JETCAS.2025.3555970(2025).

2. Z. He, Z. Cheng, Z. Xu* etc, Task-Level Parallelism for the Multifrontal Method in Tightly Coupled CPU-FPGA Architectures, 28th Annual IEEE High Performance Extreme Computing Virtual Conference(2024 Sep.).

3. P. Xu, P. Jiang, Y. Yang, X. Peng, W. Wei, T. Gong, Y. Wang, X. Long, J. Niu, Z. Xu etc, A Fully BEOL-compatible (300℃ Annealing) IGZO FeFET with Ultra Window (10V) and Prominent Endurance (10^9 ), 70 th IEEE International Electron Devices Meeting(2024 Dec.).

4. Y. Li, J. Cao , J. Yu, M. Liu, X. Zhang ,J. Chen, Q. Xu, X. Liu, J. Qiu , Y. Chen, M. Li, C. Zhu, Z. Xu, etc, Biomemristor Reservoir Computing With Multi-Value Mask for Improving Recognition Performance, IEEE Electron Device Letters, 45, 1657-1660(2024).

5. H. Tian, A. Khanaki, P. Das, R. Zheng, Z. Cui, Y. He, W. Shi, Z. Xu etc, Role of Carbon Interstitials in Transition Metal Substrates on Controllable Synthesis of High-quality Large-area Two-dimensional Hexagonal Boron Nitride Layers, Nano Lett. 18, 3352(2018).

6. A. Khanaki, H. Tian, Z. Xu* etc, Effect of high carbon incorporation in Co substrates on the epitaxy of hexagonal boron nitride/graphene heterostructures, Nanotechnology, 3, 035602(2017).

7. Z. Xu* etc, Large-area growth of multi-layer hexagonal boron nitride on polished cobalt foils by plasma-assisted molecular beam epitaxy, Sci. Reps., 7, 43100(2017).

8. A. Khanaki, Z. Xu* etc, Self-assembled Cubic Boron Nitride Nanodots, Sci. Reps., 7, 4087 (2017).  Co-first Author.

9. Z. Xu* etc, Direct growth of graphene-hexagonal boron nitride structures on cobalt foil by plasma-assisted molecular beam epitaxy, Appl. Phys. Lett, 109, 043110(2016).

10. Z. Zuo, Z. Xu* etc, In-situ epitaxial growth of graphene/h-BN van der Waals heterostructures by molecular beam epitaxy, Sci. Reps., 5, 14760(2015). Co-first Author.

11. Z. Xu* etc, Direct growth of graphene on in situ epitaxial hexagonal boron nitride flakes by plasma-assisted molecular beam epitaxy, Appl. Phys. Lett, 107, 213103(2015).

12. Z. Xu* etc, Effects of high temperature O2 annealing on Al2O3 blocking layer and Al2O3/Si3N4 interface for MANOS structure, J. Phys. D: Appl. Phys., 45, 185103(2012).

13. Z. Xu* etc, Improved performance of non-volatile memory with Au-Al2O3 core-shell nanocrystals embedded in HfO2 matrix, Appl. Phys. Lett, 100, 203509(2012).

14. Z. Xu* etc, Performance-improved non-volatile memory with aluminium nanocrystals embedded in Al2O3 for high temperature applications, J. Appl. Phys., 110, 104514(2011).


专利

1. Programming selection devices in non-volatile memory strings, US10734070B2

2. Adapting an error recovery process in a memory sub-system, US11763914B2

3. Managing execution of scrub operations in a memory sub-system, US11861178B2

4. Reliability health prediction by high-stress seasoning of memory devices, US11238950B1

5. Adaptive frequency control for high-speed memory devices, US011449377B2

6. Dynamic voltage setting optimization during lifetime of a memory device, US011740959B2

7. Selective data pattern write scrub for a memory system, WO2023034326A1

8. Rating memory devices based on performance metrics for various timing margin parameter settings, US20220137854A1

9. Adjusting read-level thresholds based on write-to-write delay, US20230050305A1

10. Managing an adaptive data path selection threshold for a memory sub-system, US20230207028A1

11. Dynamic read-level thresholds in memory systems, US20230043877A1

12. Temperature and inter-pulse delay factors for media management operations at a memory device, US11615008B2

13. Performing refresh operations of a memory device according to a dynamic refresh frequency, US20230043091A1

14. Partial block handing in a non-volatile memory device, US011901014B2

15. 一种多功能非易失存储器制备方法,CN102651233B

16. 一种多位存储器的制备方案,CN102693984B

17. 混合型非易失存储器,CN102779550B